SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect
US7671469B2 · kind B2 · utility
13Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Apr 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.