Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
US7671666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2008 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Jul 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.