System for blocking multiple memory read port activation
US7672188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Aug 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.