System and method for controlling synchronous functional microprocessor redundancy during test and method for determining results
US7673188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Sep 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a device under test (DUT) is coupled to both the gold processor and the TAP. In the first mode, the TAP provides test signals to both the gold processor and the DUT while they operate in synchronous functional lockstep. In the second mode, the TAP provides signals to the gold processor. In the third mode, the TAP provides test signals to the DUT. A host computer coupled to the interface control unit executes a software application to cause the TAP to drive test signals and to access test output data from the gold processor and the DUT. Test output data accessed from the gold processor may be compared to that accessed from the DUT to determine any differences. The comparison data generated may then be used for further analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.