Iterative method for refining integrated circuit layout using compass optical proximity correction (OPC)
US7673279B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | Feb 19, 2008 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Aug 10, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping edge fragments according to directional orientations, selecting an edge fragment or a combination of non-opposing edge fragments, calculating an edge placement error of the selected edge fragment and proximally shifting the edge fragment until a quality limitation is met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.