Semiconductor device isolation structures and methods of fabricating such structures
US7674685B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Oct 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/42
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.