Process for manufacturing a TFT device with source and drain regions having gradual dopant profile
US7674694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2008 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | May 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0321
Abstract
A process for realizing TFT devices on a substrate comprises the steps of: forming on the substrate, in cascade, an amorphous silicon layer and a heavily doped amorphous silicon layer, forming a photolithographic mask on the heavily doped amorphous silicon layer provided with an opening, removing the heavily doped amorphous silicon layer through the opening for realizing opposite portions of the heavily doped amorphous silicon layer whose cross dimensions decrease as long as they depart from the amorphous silicon layer, removing the photolithographic mask, carrying out a diffusion and activation step of the dopant contained in the portions of the heavily doped amorphous silicon layer inside the amorphous silicon layer, for realizing source/drain regions of said TFT device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.