Package-on-package semiconductor assembly
US7675152B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2005 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Sep 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are methods and devices for providing improved semiconductor packages and POP IC assemblies using the improved packages with reduced warping. According to disclosed embodiments of the inventions, a packaged semiconductor device for use in a POP assembly includes an encapsulated region generally defined by the substrate surface. The encapsulant is provided with contact apertures permitting external communication with contacts on the substrate and coupled to an encapsulated chip. Preferred embodiments of the invention are described in which the contact aperture sidewalls are angled within the range of approximately 10-30 degrees or more from vertical and in which the contact aperture is provided a gas release channel to permit gas to escape during reflow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.