Interconnect structure using through wafer vias and method of fabrication
US7675162B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2006 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Mar 20, 2027 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81B2207/092
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A device and a method are described which hermetically seals at least one microstructure within a cavity. Electrical access to the at least one microstructure is provided by through wafer vias formed through a via substrate which supports the at least one microstructure on its front side. The via substrate and a lid wafer may form a hermetic cavity which encloses the at least one microstructure. The through wafer vias are connected to bond pads located outside the cavity by an interconnect structure formed on the back side of the via substrate. Because they are outside the cavity, the bond pads may be placed inside the perimeter of the bond line forming the cavity, thereby greatly reducing the area occupied by the device. The through wafer vias also shorten the circuit length between the microstructure and the interconnect, thus improving heat transfer and signal loss in the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.