Semiconductor memory device including on die termination circuit and on die termination method thereof
US7675316B2 · kind B2 · utility
3Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | May 5, 2006 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Jul 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during n (n is positive integer) periods of a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.