On-chip detection and measurement of data lock in a high-speed serial data link
US7675966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2006 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Sep 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for on-chip detection of data lock and measurement of data lock time in a high-speed serial data link, including: permitting one or more incoming data streams into the high-speed data link; establishing a pattern to be searched in the one or more incoming data streams; comparing patterns in the one or more incoming data streams to a programmable data pattern; holding a repetitive pattern of bits in the one or more incoming data streams by one or more programmable data pattern registers, wherein when one or more occurrences of a byte are detected, an appropriate bit in the one or more programmable data pattern registers is set to indicate the byte's relative position; and filtering false indications in the repetitive pattern by using a byte detection state machine, the state machine controlling and keeping track of a search progress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.