Across-thread out-of-order instruction dispatch in a multithreaded microprocessor
US7676657B2 · kind B2 · utility
27Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2006 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Aug 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.