Spare gate array cell distribution analysis
US7676776B2 · kind B2 · utility
4Cited by
10References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Oct 28, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for determining gate array distribution includes steps or acts of: randomly placing a plurality of test boxes in a logic circuit layout; counting the number of fill cells in each of the plurality of test boxes; recording the count; grouping the plurality of test boxes into two groups: a first group with local clock buffers and a second group without local clock buffers; determining the fill cell percentage of each of the plurality of test boxes; and flagging the test boxes with a poor distribution of gate array cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.