Circuit design optimization of integrated circuit based clock gated memory elements
US7676778B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 4, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Feb 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel method for optimizing the design of digital circuits containing clock gated memory elements. The method unclock gates memory elements by adding necessary feedback loops. Logic functions of memory element outputs in the circuit are viewed as a whole, rather than as separate functions for each input. Detection of duplicate unclock gated memory elements is then effected by identifying identical canonical representations of said unclock gated memory elements. Identified duplicate clock gated memory elements can then be eliminated from the original digital circuit. Further optimization can be accomplished by applying standard logic optimization algorithms to all unclock gated memory elements in said digital circuit. The resulting optimized circuit is clock gated and replaces the original clock gated circuit in said digital circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.