Nicolas Maeding
19Patents
5h-index
36Co-inventors
62Inventor score
Filing activity: Mar 28, 2006 → Jan 25, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8046566B2 | Method to reduce power consumption of a register file with multi SMT support | Physics | 39 | Active |
| US7783690B2 | Electronic circuit for implementing a permutation operation | Physics | 10 | Active |
| US7769986B2 | Method and apparatus for register renaming | Physics | 7 | Active |
| US7890901B2 | Method and system for verifying the equivalence of digital circuits | Physics | 7 | Active |
| US7676778B2 | Circuit design optimization of integrated circuit based clock gated memory elements | Physics | 6 | Active |
| US7849428B2 | Formally deriving a minimal clock-gating scheme | Physics | 5 | Active |
| US7624363B2 | Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes | Physics | 3 | Active |
| US9506986B2 | Integrated circuit chip and a method for testing the same | Physics | 1 | Active |
| US8145804B2 | Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor | Physics | 1 | Active |
| US10317465B2 | Integrated circuit chip and a method for testing the same | Physics | 0 | Active |
| US11824984B2 | Storage encryption for a trusted execution environment | Physics | 0 | Active |
| US11755721B2 | Trusted workload execution | Physics | 0 | Active |
| US7962538B2 | Method of operand width reduction to enable usage of narrower saturation adder | Physics | 0 | Active |
| US12120222B2 | Deploying a system-specific secret in a highly resilient computer system | Electricity | 0 | Active |
| US11645092B1 | Building and deploying an application | Physics | 0 | Active |
| US12095916B2 | Chained manifest for key management and attestation | Electricity | 0 | Active |
| US10006965B2 | Integrated circuit chip and a method for testing the same | Physics | 0 | Active |
| US8370409B2 | Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing | Physics | 0 | Active |
| US8266411B2 | Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.