Patent · US Active

Buried bitline with reduced resistance

US7678654B2 · kind B2 · utility

1Cited by

14References

7Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Christoph Kleint · Dresden, DE
Clemens Fitz · Dresden, DE
Ulrike Bewersdorff-Sarlette · Radebeul, DE
Christoph Ludwig · Radeberg, DE
David Pritchard · Beacon, US
Torsten Müller · Dresden, DE
Hocine Boubekeur · Dresden, DE

Key dates

Filing date	Jun 30, 2006
Grant date	Mar 16, 2010
Priority date	—
Expiry date	Jun 17, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/18
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.