Method of making through wafer vias
US7678696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2008 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Aug 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76898
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon layer to a silicon oxide layer on the sidewalls and bottom of the trench, the silicon oxide layer not filling the trench; filling remaining space in the trench with an electrical conductor; and thinning the substrate from a bottom surface of the substrate and removing the silicon oxide layer from the bottom of the trench. The method may further include forming a metal layer on the silicon oxide layer before filling the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.