Hetero junction bipolar transistor and method of manufacturing the same
US7679105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2006 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Jan 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/852
Abstract
Provided are a hetero-junction bipolar transistor (HBT) that can increase data processing speed and a method of manufacturing the hetero-junction bipolar transistor. The HBT includes a semi-insulating compound substrate, a sub-collector layer formed on the semi-insulating compound substrate, a pair of collector electrodes disposed at a predetermined distance apart from each other on a predetermined portion of the sub-collector layer, a collector layer and a base layer disposed between the collector electrodes, a pair of base electrodes disposed at a predetermined distance apart from each other on a predetermined portion of the base layer, an emitter layer stack disposed between the base electrodes, and an emitter electrode that is formed on the emitter layer stack, and includes a portion having a line width wider than the line width of the emitter layer stack, wherein both sidewalls of the emitter electrode are respectively aligned with inner walls of the pair of base electrodes, and sidewalls of the collector layer and the base layer are located between outer sidewalls of the pair of base electrodes of the pair of base electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.