Semiconductor device

US7679138B2 · kind B2 · utility

Assignee

• Renesas Technology Corporation · JP

Inventor

• Mikio Tsujiuchi · Tokyo, JP

Key dates

• Filing date: Apr 10, 2007
• Grant date: Mar 16, 2010
• Expiry date: Mar 5, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A MOS transistor including a source region, a drain region, and a gate electrode has first and second partial isolation regions in one-end gate region and the other-end gate region, respectively, with a first tap region provided adjacent to the first partial isolation region, and a second tap region provided adjacent to the second partial isolation region. A full isolation region is provided in the whole area around the first and second partial isolation regions, first and second tap regions, and source and drain regions.