Memory device having selectively decoupleable memory portions and method thereof
US7679974B2 · kind B2 · utility
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13References
11Claims
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Key dates
| Filing date | Oct 19, 2006 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Nov 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to determining a bit cell of a bit cell array of a memory device is a defective bit cell, a portion of the bit cell array including the defective bit cell is decoupled from a power source of the memory device. The portion can be decoupled via a fuse, a transistor, and the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.