DMA controller configured to process control descriptors and transfer descriptors
US7680963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2007 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Nov 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.