Patent · US Active

Clock data recovery circuit with circuit loop disablement

US7681063B2 · kind B2 · utility

4Cited by

8References

26Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Hamid Partovi · Sunnyvale, US
Luca Ravezzi · San Francisco, US
Karthik Gopalakrishnan · San Jose, US
Andreas Blum · Reutlingen, DE
Paul Lindt · Donauwörth, DE

Key dates

Filing date	Mar 30, 2005
Grant date	Mar 16, 2010
Priority date	—
Expiry date	Jan 12, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/093
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the data. The second circuit is configured to receive the first signal and provide a first shift signal based on the first signal. The third circuit is configured to receive the first shift signal, wherein the first circuit, the second circuit, and the third circuit are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and shift the clock signal based on the first shift signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.