Systems and methods for improved fault coverage of LBIST testing
US7681098B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 20, 2006 |
| Grant date | Mar 16, 2010 |
| Priority date | — |
| Expiry date | Sep 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) by determining weighting and/or seed values to be used in generating pseudorandom test bit patterns for each channel to optimize fault coverage. In one embodiment, a method includes generating a pseudorandom sequence of bits, applying a weighting value to the sequence, propagating the weighted sequence through one or more levels of logic, and capturing the resulting data. Metrics are then applied to the captured data to determine the suitability or optimality of the weighting value, and an optimal weighting value is selected. This may be performed for a plurality of trial values for each of a number of channels to obtain a set of weighting values for the different LBIST channels. The method may also include determining a seed value for the pseudorandom bit pattern generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.