Dynamic control of back gate bias in a FinFET SRAM cell
US7681628B2 · kind B2 · utility
118Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2006 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jun 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based on an operational mode (e.g., Read, Half-Select, Write, Standby) of the SRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.