Method for fabricating vertical channel transistor in a semiconductor device
US7682885B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jun 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/025
Abstract
A method for fabricating a semiconductor device includes forming a sacrificial layer over a substrate, forming a contact hole in the sacrificial layer, forming a pillar to fill the contact hole. The pillar laterally extends up to a surface of the sacrificial layer and then the sacrificial layer is removed. The method further includes forming a gate dielectric layer over an exposed sidewall of the pillar, and forming a gate electrode over the gate dielectric layer. The gate electrode surrounds the sidewall of the pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.