Methods of forming NMOS/PMOS transistors with source/drains including strained materials
US7682888B2 · kind B2 · utility
2Cited by
12References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 2006 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jul 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02293
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a <100> crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.