Method and structure for double lining for shallow trench isolation

US7682929B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Liu Chi-Kang · Shanghai, CN
• Xin Wang · Tianjin, CN
• Ze Ki Li · Shanghai, CN

Key dates

• Filing date: Sep 28, 2006
• Grant date: Mar 23, 2010
• Expiry date: Jul 17, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76232
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming an integrated circuit device structure having a design rule of less than 0.13 micron. The method includes providing a substrate and forming a pad oxide layer overlying the substrate. The method includes forming a nitride layer overlying the pad oxide layer and patterning the nitride layer and pad oxide layer. A trench structure is formed within a thickness of the substrate using the patterned nitride layer and pad oxide layer as hard mask. The method forms a first thickness of liner oxide within the trench structure using at least thermal oxidation of an exposed region of the trench structure to cover the trench structure. Such thermal oxidation causes a rounding region near corners of the trench structure. The method selectively removes the thickness of liner oxide within the trench structure. The method forms a second thickness of liner oxide within the trench structure using at least thermal oxidation to cover the trench structure. The thermal oxidation causes a further rounding of the rounded region near corners of the trench structure. The method also selectively removes the patterned nitride layer while the second thickness of liner oxide protects the subs…