MOS transistors having recesses with elevated source/drain regions
US7683405B2 · kind B2 · utility
12Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2004 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Aug 17, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
Metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions and methods of fabricating the same are provided. The MOS transistors may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.