Electronic component unit
US7683482B2 · kind B2 · utility
50Cited by
26References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2006 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Nov 7, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.