Phase locked loop circuits, offset PLL transmitters, radio frequency integrated circuits and mobile phone systems
US7683723B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Feb 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/185
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.