Flash memory device and method of erasing memory cell block in the same
US7684254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2006 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Mar 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.