Method and apparatus for implementing FIFOs using time-multiplexed memory in an integrated circuit
US7684278B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2008 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Aug 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for implementing first-in-first-out (FIFO) memories using time-multiplexed memory in an integrated circuit are described. A block random access memory (BRAM) circuit embedded in the integrated circuit is provided. The BRAM includes at least one port responsive to a respective at least one BRAM clock signal. FIFO logic is configured to implement a plurality of FIFOs in the BRAM having a plurality of interfaces. Multiplexer logic is configured to selectively couple the plurality of output interfaces of the FIFO logic to the at least one port of the BRAM circuit responsive to at least one FIFO clock signal. Each of the at least one BRAM clock signal has at least twice the frequency of a respective one of the at least one FIFO clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.