Histogram generation with banks for improved memory access performance
US7684280B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jun 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1071
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dividing memory used for storing histogram data into multiple banks is disclosed to allow for phased RMW cycles. Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be started in one bank while the previous RMW cycle is still being performed in another bank. By staggering or phasing the starts of the RMW cycles in a wraparound fashion, each histogram bin is spread out over multiple banks, but testing can proceed faster than if only a single bank was used. After the histogram data has been captured, the areas of memory in each bank associated with a particular bin can be added together to compute the total count for that bin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.