Method and apparatus for handling of clock information in serial link ports
US7684534B2 · kind B2 · utility
10Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2006 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Oct 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.