Fast-carry arithmetic circuit using a multi-input look-up table
US7685215B1 · kind B1 · utility
6Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2005 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jan 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, programmable circuits, such as FPGAs, may be used to implement different types of functions, such as a multi-bit adder, using look-up table (LUT) circuits as their building blocks. Efficient generation of carry-out signals and fast-carry generation signals using available SRAM cells in the various embodiments of the LUT circuit can reduce and/or eliminate area-inefficient look-ahead carry logic without a significant delay in signal generation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.