Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirects
US7685410B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2007 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jan 17, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor comprises a branch resolution unit and a redirect recovery cache. The branch resolution unit is configured to detect a mispredicted branch operation, and to transmit a redirect address for fetching instructions from a correct target of the branch operation responsive to detecting the mispredicted branch operation. The redirect recovery cache comprises a plurality of cache entries, each cache entry configured to store operations corresponding to instructions fetched in response to respective mispredicted branch operations. The redirect recovery cache is coupled to receive the redirect address and, if the redirect address is a hit in the redirect recovery cache, the redirect recovery cache is configured to supply operations from the hit cache entry to a pipeline of the processor, bypassing at least one initial pipeline stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.