Two parallel engines for high speed transmit IPsec processing
US7685434B2 · kind B2 · utility
13Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2004 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Oct 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/164
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, and a security system. The network interface offloads IPsec processing from the host processor. According to the invention, the security system includes two processors for encrypting and authenticating the outgoing data. Outgoing data packets are sent alternately to one or the other processor, whereby transmission processing can be accelerated relative to receive processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.