Bitmap cluster analysis of defects in integrated circuits
US7685481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2005 |
| Grant date | Mar 23, 2010 |
| Priority date | — |
| Expiry date | Jan 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for defect analysis are disclosed wherein a defect data set is input into the system. A radius value is selected by a user, which is the maximum number of bits that bit failures can be separated from one another to be considered a bit cluster. When a defect data set is received, the system and method start with a fail bit and search for neighboring fail bits. The specified radius is used to qualify the found fail bits to be part of the bit cluster or not. If a minimum count of fail bits is not met, the system and method will stop searching and move to the next fail bit. If a minimum count of fail bits is met, the search continues for the next fail bit until the maximum fail bit count specified by the user is reached. Aggregation is provided such that once bit clusters have been classified, the number of clusters that have the exact match or partial match to each other is counted. The user may set the partial match as a threshold count to establish a match.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.