Functional failure analysis techniques for programmable integrated circuits

US7685485B2 · kind B2 · utility

Assignee

• Altera Corporation · US

Inventors

• Binh Vo · Los Gatos, US
• Wan-Pin Hung · Saratoga, US
• David Huang · Melbourne, AU
• Peter Boyle · Mountain View, US
• Qi Richard Chen · Sunnyvale, US
• Kaiyu Ren · San Jose, US
• Adam Wright · Santa Clara, US
• John DiCosola · Pleasanton, US
• Laiq Chughtai · San Jose, US
• Seng Yew Lim · Bukit Mertajam, MY

Key dates

• Filing date: Oct 30, 2003
• Grant date: Mar 23, 2010
• Expiry date: Dec 24, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318516
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.