Patent · US Active

Method for designing integrated circuits comprising replacement logic gates

US7685550B2 · kind B2 · utility

2Cited by

5References

19Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Sascha Siegler · Unterhaching, DE
Roswitha Deppe · Munich, DE
Georg Georgakos · Fraunberg, DE

Key dates

Filing date	Feb 24, 2006
Grant date	Mar 23, 2010
Priority date	—
Expiry date	Apr 6, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/39
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In a method for designing integrated circuits comprising replacement logic components, a plurality of logic cells and a plurality of filler cells which fill interspaces between the logic cells are positioned on a chip area. In this case, some or all of the filler cells represent replacement logic components for the integrated circuit and have been or are interconnected or wired in such a way that they form capacitances in the integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.