Method of reducing embedded SiGe loss in semiconductor device manufacturing

US7687338B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Sameer H. Jain · Beacon, US
• Shreesh Narasimha · Beacon, US
• Karen A. Nummy · Newburgh, US
• Viorel Ontalus · Danbury, US
• Jang Sim · Beekman, US

Key dates

• Filing date: Dec 5, 2007
• Grant date: Mar 30, 2010
• Expiry date: Jan 30, 2028

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.