Low-k isolation spacers for conductive regions

US7687364B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventor

• Bernhard Sell · Dresden, DE

Key dates

• Filing date: Aug 7, 2006
• Grant date: Mar 30, 2010
• Expiry date: Sep 7, 2028

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall of a gate electrode in a MOS-FET device.