Method of forming fine metal patterns for a semiconductor device using a damascene process
US7687369B2 · kind B2 · utility
4Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Feb 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32134
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.