Patent · US Active

Method of forming silicided gates using buried metal layers

US7687396B2 · kind B2 · utility

2Cited by
1References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 29, 2006
Grant dateMar 30, 2010
Priority date—
Expiry dateApr 15, 2027

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/28097
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.