Front-end processed wafer having through-chip connections
US7687397B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Apr 5, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | May 30, 2027 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C1/00095
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metallization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.