Method for reducing line edge roughness for conductive features
US7687407B2 · kind B2 · utility
1Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2005 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | May 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion (510) of a substrate (220) to a first etch process, the first etch process designed to etch at a first entry angle (θ1), and subjecting a second portion (610) of the substrate (220) to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (θ2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.