Silicon-alloy based barrier layers for integrated circuit metal interconnects
US7687911B2 · kind B2 · utility
5Cited by
1References
5Claims
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Key dates
| Filing date | Sep 7, 2006 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | May 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a silicon alloy based barrier layer comprises providing a substrate having a dielectric layer including a trench, placing the substrate in a reactor, and carrying out a process cycle, wherein the process cycle comprises introducing a silicon containing precursor into the reactor, introducing a metal containing precursor into the reactor, and introducing a co-reactant into the reactor, wherein the silicon, metal, and co-reactant react to form a silicon alloy layer that is conformally deposited on a bottom and a sidewall of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.