Semiconductor device and a method of manufacturing the same and designing the same
US7687914B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Sep 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.