Fabrication method of semiconductor integrated circuit device and probe card
US7688086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2006 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Nov 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/07314
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
To provide a technique of firmly bringing a stylus and a test pad into contact with each other in carrying out a probe testing summarizingly for plural chips by using a prober having the stylus formed by a technique of manufacturing a semiconductor integrated circuit device, plane patterns of respective wirings are formed such that a wiring and a wiring electrically connected to the wiring or a wiring which is not electrically connected to the wiring overlap each other, and a plane pattern arranged with both of the wiring and the wiring is constituted at upper portions of probes. Further, patterns of the wirings are formed such that an interval of arranging the wirings and a density of arranging the wirings become uniform at respective wiring layers in a thin film sheet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.