Semiconductor memory device with debounced write control signal
US7688649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2008 |
| Grant date | Mar 30, 2010 |
| Priority date | — |
| Expiry date | Mar 10, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a memory cell array, an input buffer, an output buffer, and an input-output control circuit that receives a write control signal and controls the input and output buffers. The output buffer generates a commencement signal indicating commencement of output. A mask generating circuit generates a mask signal with delayed active-to-inactive transitions from the commencement signal. A masking circuit passes the write control signal to the input-output control circuit while the mask signal is inactive, and holds the write control signal in the write-disabling state while the mask signal is active. The mask signal prevents unintended writing of data in the memory cell array when the write control signal is contaminated by noise from the output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.